Talk:Flip-flop (electronics)

Slow down top animation ("R-S mk2.gif")?

Any chance of slowing down the animation, so that the transition between the stable states can be followed? — Preceding unsigned comment added by 91.125.194.28 (talk) 22:47, 13 February 2013 (UTC)

New animated diagram

A True frequency divisor. Not relying on any timing or capacitors

This diagram is busy, hard to interpret, unsourced, probably original research. It was added today, but I took it out and brought it here because I don't see how it adds anything useful or appropriate to the article. Other opinions? Dicklyon (talk) 19:46, 23 March 2013 (UTC)

• Yes, it is too busy. Glrx (talk) 01:28, 24 March 2013 (UTC)
• I agree, it's badly illustrated and much too busy. Also, it does not really add anything to the article. --Matthiaspaul (talk) 20:35, 31 March 2013 (UTC)
• Well, you mean that it is original "research" just because I drew it in reaction to the buggy JK-Flipflop-diagram in the german version. I could lower the speed, but perhaps I should show each single motion, not the stable end-states only. Perhaps some effect, too, when the gate switches. Ohnemichel (talk) 12:15, 7 April 2013 (UTC)

Well, the main question is if we need a complex diagram like this in what is mostly an introduction article about flip-flops. Perhaps we should first add actual contents to the article to bring the reader to a level that s/he will comprehend the diagram? Perhaps the diagram would be better suited in an article about logic state machines or such.

Another point is that the drawing can be improved significantly, IMHO. Here are some general guidelines how to draw easy to understand and non-ambiguous schematics:

• Use only horizontal and vertical signal wires (in rare cases 45° angles may be allowed as well, but try to avoid them elsewhere).
• When you connect a signal wire to a gate's pin, there should always be at least a small wire stub in the pin's direction (that is, no angled wires on pins).
• Never draw wires over parts or pins (unless there's a connection, but then see above).
• Never double-use pins as wire junctions (that is, there should be only one wire going to a particular pin).
• Rearranging the gates a bit you could make symmetries much more visible.
• Properly label gates, pins and signals.
• Explicitly declare inputs and outputs.

Hope it helps. --Matthiaspaul (talk) 17:27, 7 April 2013 (UTC)

And we really need to cite a source for this circuit, and for the notion of a "True frequency divisor". To me the biggest problem with the animation is that color changing is a very poor motion cue; it's hard to see what is causing what. If the color difference had more luminance contrast it would be easier to follow; if it flowed along the wires, it would help the viewer follow the causality. But it's going to hard to make it a sensible animation, I think. Dicklyon (talk) 17:38, 7 April 2013 (UTC)

Possible mistake at JK latch

At JK latch "Unlike the JK flip-flop, the 11 input combination for the SR latch is not useful because there is no clock that directs toggling." Shouldn't it be "JK latch is not useful"? — Preceding unsigned comment added by 89.136.163.200 (talk) 12:28, 13 December 2013 (UTC)

No, the J=K=1 condition has the useful property of making the JK behave as a toggle (T) latch. SpinningSpark 00:49, 20 December 2013 (UTC)

Uh, toggle latch? There's a toggle FF, and holding J=K=1 turns a JK FF into a T flop.

Commons has a schematic for a JK latch, but it looks like J and K have been swapped. If Q = 1, then the K input should be be enabled so that it can drive Q to zero.

I'd say the JK latch with 11 inputs isn't useful, but maybe somebody wants a racy pulse generator / freely toggling output that some versions might provide.

Glrx (talk) 00:51, 21 December 2013 (UTC)

Hmm, you are right, hadn't read the article properly. Seems to me an unclocked JK latch is not especially useful period. Is this just an intermediate form for the purpose of teaching the subject? Don't think one can buy such a latch. SpinningSpark 02:15, 21 December 2013 (UTC)

It may make sense when some form of narrow-pulse logic is used. Discrete T-flops were made with a diode-clamped differentiator (to generate a narrow positive pulse) and some diodes gating to route the pulse to the cutoff transistor. A narrow positive pulse delivered simultaneously to J and K inputs would cause it to toggle; if the pulse is too wide, the result would be indeterminate. Glrx (talk) 20:21, 26 December 2013 (UTC)

Historical Contributions by Claude Shannon?

It appears the RS flip-flop appears on page 30 of Claude Shannon's 1940 Master's Thesis, as what he calls a "lock-in" circuit:

http://mondrian.die.udec.cl/~mmedina/Clases/SistDig/Shannon%20-%20A%20Symbolic%20Analysis%20of%20Relay%20and%20Switching%20Circuits.pdf

latch vs. flip-flop

So I don't _think_ it is common any longer (if ever) to refer to an SR-latch as a type of flip-flop. Modern taxonomy has flip-flops as edge triggered devices, which an SR-latch certainly is not. Wakerly, Vahid, and others [1], [2] [3] make that definition pretty clear. Any objections to cleaning this up? (Not that I have time to do that right now, but it's really annoying me...) Hobit (talk) 21:50, 26 January 2017 (UTC)

It certainly was common for a long time to treat latches as a subset of flip-flops, and edge-triggered as another subset. Has this changed? Dicklyon (talk) 22:15, 26 January 2017 (UTC)

• I follow Dicklyon's viewpoint: the whole class of bistable elements are flip-flops; as the article says, transparent FFs are commonly called latches. I don't see a clear exclusion between "latch" and "flip-flop". I think somebody who grew up on TTL calls a '373 a D-latch and a '374 a D-flip-flop, but I don't think that means a latch is not a FF. Discrete 2-transistor SR flip-flops used diode steering and RC differentiators to achieve edge-triggered toggling. Von Neuman's machine may have used more bizarre gating to capture state changes, but my memory fails me (common-cathode triggering?); it might be in Dyson's Turing's Cathedral (see page 125 where Bigelow used "toggle" instead of FF). The 1964 GE Transistor Manual has index entries for "flip-flop" but not for "latch". The classic state machine used a narrow clock pulse (rather than a clock edge) to quickly capture the D inputs before the inputs had a chance to change (dynamic timing); I think those "latches" were called "flip-flops". Components were too expensive for static designs, so there wasn't a need to distinguish between latch and FF in the early days. With two-phase clocking, it makes sense to call the transparent bistable element a latch. The now common edge-triggered flip-flop is the master-slave cascade of two level-sensitive flip-flops (I don't think they were called master and slave latches in the TI TTL databook). ECL designers made the distinction between level-sensitive latches and edge-sensitive flip flops because speed and clocking were important; ECL designers would not waste pipeline stages using an edge-sensitive flip-flops. Glrx (talk) 23:56, 26 January 2017 (UTC)

  I looked at some of the books he cited, and I can see what's causing the confusion, which is that the books mostly admit the terminology is mixed and confusing, and then say what they adopt for their book, which is the latch versus flip-flop distinction he describes. However, that's a narrow view based on the small subset of flip-flop styles they're teaching. We should probably mention that modern logic viewpoint, but not throw out the general term of flip-flop in favor of such narrow uses. Dicklyon (talk) 01:50, 27 January 2017 (UTC)

  By the way, I have every edition of the GE transistor manual and could check on how they treat flip flops. If memory serves, the second edition may have been the first to mention them; I forget what year that was, but I remember as a kid being completely stymied by their step-by-step instructions on how to design a flip flop, at step 1 "choose R_L" or something like that; I eventually made one work. Dicklyon (talk) 01:53, 27 January 2017 (UTC)

A master/slave configuration is almost certainly not the most common flip-flop. A master/slave uses 8 gates compared to 6 gates for an edge-triggered circuit that uses a race to disable the inputs. In the 70s, when I used to do gate-level chip design at IBM, we used either latches with two-phase clocks or edge-triggered 6-gate FFs in our designs. I cannot recall ever seeing anyone design anything with a master/slave FF. Why would anyone deliberately waste the extra 2 gates? So far as I can tell (and I say this as a university lecturer who now teaches digital design), the only reason we teach master/slave is because it's easier to explain than edge-triggering to students new to the subject. Msnicki (talk) 03:10, 27 January 2017 (UTC)

Latches used to be called flip-flops but this is no longer current convention. For example, I have a copy of E.J. McCluskey's famous Introduction to the Theory of Switching Circuits (1965) that served as our text when I took logic design from McCluskey himself at Stanford in 1971. It never uses the term latch at all, consistently calls latches (made with vacuum tubes) flip-flops, and never even mentions master/slave and edge-triggered circuits. The world has clearly changed since then.

I think it would be appropriate to mention the historical confusion of the terms but to be clear about modern usage. Today, latches are not considered to be flip-flops. A flip-flop is an edge-triggered circuit created using a master/slave configuration or with a race to disable the inputs. I think the article should make that clear. Msnicki (talk) 02:55, 27 January 2017 (UTC)

I agree we need to make the modern terminology clear. But I can't agree that "Today, latches are not considered to be flip-flops." They are still bistable memory elements, which is what the term flip-flops most generally denotes. Btw, I was at Stanford a few years after you, but didn't take McCluskey's class; I was doing all edge-triggered TTL by then, but a latch never became not a flip-flop as far as I can see. Dicklyon (talk) 03:01, 27 January 2017 (UTC)

Brown & Vranesic's (very popular) Fundamentals of Digital Logic with Verilog Design, Third Edition (2014), which we use at UW, consistently makes a clear distinction between latches and edge-triggered FFs. From page 258, "The term flip-flop denotes a storage element that changes its output state at the edge of a controlling clock signal." I'm convinced this is current convention. A latch is no longer considered a flip-flop. Msnicki (talk) 03:32, 27 January 2017 (UTC)

On the one hand, yes, I agree this is current convention. But I don't think that goes so far as to make a latch not a flip-flop, just because flip-flop is conventionally taken to mean edge-triggered flip-flop. I think we can explain this in the article, stating current conventions, but not saying that a latch is not a flip-flop (except when those conventions are accepted). Dicklyon (talk) 03:38, 27 January 2017 (UTC)

You have my head spinning, Dick. If a FF is now defined as an edge-triggered device and a latch is not edge-triggered, it doesn't sound to me like a latch can possibly be a FF. I think the world has moved on from the usage that you and I remember from the 70s. Msnicki (talk) 03:46, 27 January 2017 (UTC)

Not within that definition, no. The point is that the modern definition does not make the old definition go away; we need to discuss the distinction, neutrally. Even those who define flip-flop the way you say probably don't go so far as to say that a latch "is not a flip-flop" in an absolute sense, do they? It's still a type of flip-flop, just not the type they mean. Dicklyon (talk) 04:01, 27 January 2017 (UTC)

Well, this textbook sure seems to say that. If that chance to meet we've talked about the next time you're in Seattle happens, I'll bring it along for inspection. Msnicki (talk) 04:14, 27 January 2017 (UTC)

On reflection, it seems to me the essence then and now is that a FF is clocked device that can change state at most once per clock. As Glrx observed, what's changed is how we do it. Originally, it was done with narrow clock pulses as a way to disable the input before it could change. No one does that anymore. We use edge-triggering. But I don't think anyone then or now expected a FF was something that could behave like a ring oscillator anytime you hit it with a clock and might settle in an unpredictable state. Assuming tsetup and thold are met, a FF that makes more than one state change per clock and can settle randomly is not a FF and never has been. Msnicki (talk) 18:22, 27 January 2017 (UTC)

• Yeah, I'd claim (and the sources I cited back up) the idea that the term flip-flop and latch have changed over time. I don't go back as far as you two, but far enough to remember when the terminology was more mixed than it is today. I teach and work with researchers in this area, and even the older folks largely use the the more modern terminology (and always use it when teaching AFAICT). Hobit (talk) 14:11, 27 January 2017 (UTC)

• "Why would anyone deliberately waste the extra 2 gates? So far as I can tell (and I say this as a university lecturer who now teaches digital design), the only reason we teach master/slave is because it's easier to explain than edge-triggering to students new to the subject." Clock skew. Glrx (talk) 20:37, 27 January 2017 (UTC)
  • I also teach it that way and for the same reason. There are lots of ways to build flip-flops, but it's not all that important to teach more than one in an undergraduate class. Hobit (talk) 22:07, 27 January 2017 (UTC)

MS FFs have shorter tHold times so they should be more tolerant of clock skew but they're not going to make the problem go away. Am I overlooking something? Are there applications where designers are typically better off with MS FFs, rather than edge-triggered? Msnicki (talk) 22:29, 27 January 2017 (UTC)

Sorry, I'd missed the clock skew part of Glrx's comment. I teach MS because it's a lot easier to teach and for the students to understand. At that level, there isn't any hugely important reason for students to understand Dff variants (IMO). Hobit (talk) 02:58, 29 January 2017 (UTC)

I'm not sure the issue is understood; I'm not particularly concerned with tHold. What does a designer do when tSetup+tHold+tProp << clock skew? With simple D FFs, some FFs will have changed before others know there was a clock. MS allows one to set tProp. It's a two-phase clock with no computation during Φ2. Think about the lengths (and power) designers go to minimize clock skew. IIRC, a chip may burn half its power on clock distribution. Glrx (talk) 02:56, 30 January 2017 (UTC)

I don't see how that offers much advantage. If the whole point is that you'd like to delay how fast a clock edge could propagate back to an input (yes, a valid way to cope with skew), why not just add extra buffers as necessary to lengthen any critical paths from Q → D that aren't already long enough? Seems to me the Verilog compiler could do that for you. The reason clocks burn so much power is because they change at (guess what) the clock frequency and they drive everything. Other signals don't change as often and they don't have as many loads. Digital circuits only burn significant power during transitions (the so-called speed-power product). That's the only time they're in the active region. In the 1 or 0 states, they're in cutoff or saturation. Msnicki (talk) 05:46, 30 January 2017 (UTC)

Not going to weigh in on the rest of this (I don't know enough), but static power consumption (power used when nothing is changing) has become a major issue over the last 15 years in high-end designs. To make the devices fast, they tend to have fairly high leakage currents. Static power can reach 50% of total power pretty easily. [4] has an analysis of a couple of devices (though I don't know that I quite buy the methodology). Hobit (talk) 17:05, 31 January 2017 (UTC)

Very interesting. I did not know that. This article suggests it's the small features causing the problem. Msnicki (talk) 03:34, 1 February 2017 (UTC)

Indeed, as features scale down, oxide thickness has to scale down, too, and it gets to where tunneling current is significant (more than the S-D leakage, iirc). This is the mechanism predicted to limit Moore's law scaling about 45 years ago in FUNDAMENTAL LIMITATIONS IN MICROELECTRONICS - I. MOS TECHNOLOGY by Hoeneisen and Mead. Dicklyon (talk) 05:55, 1 February 2017 (UTC)

Yep, though keep in mind the oxide thickness doesn't _have_ to scale down. One can increase the threshold voltage and thus decrease the static power, though that slows down the transistor. One interesting idea (implemented in the real world but still being researched I think) is to have slower transistors wherever you can. They are already in places like caches, but picking individual transistors in a design to resize is also a thing though I don't know what the current state-of-the-art is. Hobit (talk) 11:49, 1 February 2017 (UTC)

• Back to the original question: do any objections to my original proposal remain? If not, I may try to work on this over the next few weeks. Hobit (talk) 16:50, 3 February 2017 (UTC)

Where is the proposal? I'm OK with cleaning up to explain that in modern terminology flip-flop usually means edge-triggered, but I would object to anything saying that a latch is not a flip-flop in the more generic and historic meaning of the term. It shouldn't be hard to keep this neutral and represent the evolving interpretation of the term in different contexts. Dicklyon (talk) 17:08, 3 February 2017 (UTC)

I think in modern terminology flip-flop always means edge-triggered. Always. I've continued to review other current textbooks using Google books and I cannot a single one that still calls a latch a flip-flop. If you know of a textbook published in, say, the last decade or so that disagrees, a citation would be helpful. I think we should confine any description of a latch as a flip-flop to a section on the history of these devices, explaining that a latch used to be called a flip-flop, but only because clocking was done with short pulses that ensured only a single change per clock. There is no point in having an article that reports out-of-date information as if it was still current. Msnicki (talk) 18:43, 3 February 2017 (UTC)

The place where the conventional old broader meaning of flip-flop is still common in current publications is in describing SRAM bit cells; Here are some of the most recent books. These are more like what you'd call latches, but any bistable element is properly a flip flop. Some books do still list latches as types of flip flops (in the 21st century that is): 2006, 2015. But yes they are getting to be more sparse. Dicklyon (talk) 23:16, 3 February 2017 (UTC)

I'm not convinced, Dick. Your first link is to a Google search, not to any specific textbook. And your other two books don't actually support your claim that it's still current terminology to call a latch a flip-flop. The "2006" book is actually a 4th edition of book published in 1985. That's over 30 years ago. I concede that 30 years ago, the terms were confused. The question is what about now.

And while your 2015 book does say that latches "form one class of flip-flops", the author immediately distances himself from that position by stating, "The simple flip-flops are commonly called latches. The word 'latch' is mainly used for storage elements, where as [sic] clocked devices are described as 'flip-flops'. Latches are level-sensitive whereas flip-flops are edge-sensitive." Further, I'm genuinely skeptical that this book qualifies as a textbook or would be used as such at any university. In the preface, it states, that "The book Digital Electronics -- GATE, PSUs and ES Examination has been designed after much consultation with the students preparing for these competitive examinations." These are exams specific to India where the book was published.

I remain unconvinced that current textbooks actually used at the university level call latches flip-flops. I think we have to go with the preponderance of reliable sources and that that preponderance is very clear: Latches are no longer considered flip-flops. But again, I do support explaining the historical usage. Msnicki (talk) 00:16, 4 February 2017 (UTC)

I think that saying "The simple flip-flops are commonly called latches" is the basic strategy we need to pursue here, as some books do. They're called latches, but that doesn't make them no longer flip-flops. On the SRAM search, I'm sure you can see in the snippets that there are lots of recent books calling the bistable SRAM cells flip-flops. I have nothing against the preponderance of current sources, except that if we use them to rewrite or ignore historical definitions as if they never existed, that would be bad, and would disconnect from current terminology in the SRAM area, and probably in some other areas. So proceed with care, is all I'm saying. Dicklyon (talk) 02:19, 4 February 2017 (UTC)

Okay, since you insist, I went through the entire list on those two pages of all 14 Google search results on SRAMS. Not a single one of them is convincing. Four of them don't even mention flip-flops. The best of the bunch is Cryptographic Hardware and Embedded Systems [5] but it doesn't call latches flip-flops, it refers to using a flip-flop in the control circuitry, c.f., Fig 4 on page 515, which clearly shows a edge-triggered D-FF used to control the WL (write line) going to the cells. It does not call the cells flip-flops. Emerging Memory Technologies[6] says the same thing, that SRAM uses a flip-flop controller. Four of the books [7], [8], [9], [10] do claim that SRAM uses flip-flops to store data but none appear authoritative to me. The titles of the first two, Practical Electronics for Inventors and Teach Yourself Electricity and Electronics, speak for themselves. The other two are study guides. Clearly, none of these are textbooks and in the face of numerous actual current textbooks that clearly and pointedly disagree, I would not trust any of them as reliable sources to support your claim that latches are still called flip-flops. Msnicki (talk) 04:04, 4 February 2017 (UTC)

I of course am on the same page here. (Disclaimer: Msnicki and I now have work-related real-life interactions that started due to this discussion. They will last for at least the next couple of weeks. As such I'll slow down on comments here for a bit.) Hobit (talk) 17:33, 5 February 2017 (UTC)

Low-quality external links

A couple more external links just got added today, prompting me to check the whole list. To me, they all look like low-quality junk. Does anyone have an objection if I remove them all? Msnicki (talk) 05:27, 4 February 2017 (UTC)

CMOS implementation of an edge-triggered D-flip flop

Anyone care to explain how this circuit functions / provide sources ? It comes without any explanations, and hand analysis + simulations don't show it working. Besides it doesn't have any feedback loop, so I fail to see how it could act as a sequential system ? NoahhaoN (talk) 01:37, 18 May 2017 (UTC)

I agree. It looks wrong. It has no feedback so the only way it can save a bit value is by charging a stray capacitor, but I can't see where that would be. A correct CMOS D flip-flop is shown at http://www.learnabout-electronics.org/Digital/dig55.php figure 5.5.2. I think the illustration must be changed and the text should emphasize that it is specific for CMOS technology - it doesn't work with bipolar transistors. Agnerf (talk) 11:42, 21 August 2018 (UTC)

I moved it into the dynamic section. Dicklyon (talk) 23:56, 5 January 2019 (UTC)

SR NOR latch

Recent edits show a problem at Flip-flop (electronics)#SR NOR latch which currently ends with:

Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch.

Characteristic: Q+ = R'Q + R'S or Q+ = R'(Q + S).

I believe R' means not R = R, and Q+ refers to what is called Q_next in the table. That is,

Characteristic: Q+ = RQ + RS or Q+ = R(Q + S).

That seems wrong; it should be:

Characteristic: Q+ = QS + QR.

Thoughts? Johnuniq (talk) 23:22, 4 November 2017 (UTC)

Multi-bit Latch vs single-bit flip-flop. Edge-trigger designation.

The term flip-flop is not consistently used to differentiate edge triggered from level triggered devices, but the term flip-flop has always consistently referred to a single bit storage element constructed from logic gates. The term latch has historically been used for multiple bit storage elements that share a trigger. The terms edge triggered and level triggered are clear and unambiguous and should be used to differentiate between the triggering mechanism, rather than trying to use flip-flop for that purpose. "Level triggered flip-flop" can be found in textbooks from the 70's, and changing the terminology makes reading older material misleading. It's clearer to stick with the original designations:

References

Edge triggered flip-flops

• clearly a single bit
• clearly edge triggered

Level triggered flip-flops

• clearly a single bit
• clearly level triggered

Edge triggered Latches

• clearly edge triggered
• may store multiple bits

Level triggered Latches

• clearly level triggered
• may store multiple bits

Use of this terminology is historically consistent and unambiguous. Also, because multi-bit latches exist, they should have their own page. The internals of storage of each bit should direct to the flip-flop page.

132.160.49.90 (talk) 22:41, 5 January 2019 (UTC)Dr. T.S. U.of H. Jan 2019

I support this suggestion. At least parts of it agree with the 2013 update of the referenced text. Dicklyon (talk) 23:41, 5 January 2019 (UTC)

I agree flip-flop is one bit. I don't think the rest is even vaguely standard. Usually for multi-bit flip-flops the term "register" is used. Hobit (talk) 02:47, 16 September 2021 (UTC)

Q and Q-bar do not switch exactly simultaneously

In latches and flip flops Q and Qbar do not change signal exactly simultaneously. Should this fact be added to the article, together with it's consequences? Jacob.Koot (talk) 11:12, 15 May 2021 (UTC)

Latches vs Flip-flops again

I'd like to clean up this issue. As noted above, the interchangeable use of "latch" and "flip-flop" hasn't been standard for probably decades. If needed we can have a formal RfC, but I thought just see if we can agree to use latch for the transparent/asynchronous devices and flip-flop for the synchronous edge-triggered devices. Objections? Hobit (talk) 02:46, 16 September 2021 (UTC)